When scaling for next generation complementary metal-oxide semiconductor (CMOS) devices in connection with increased miniaturization, including, for example, very-large-scale integration (VLSI), middle-of-the-line (MOL) resistance can be a critical issue affecting device performance. Scaling of CMOS devices calls for independently reducing contact resistance of both n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs), which requires different silicides for NFETs and PFETs, to independently achieve low contact resistance on both an NFET and a PFET, respectively.
CMOS technology is widely utilized to fabricate circuits for various types of applications. For example, for memory applications, CMOS technology is utilized to fabricate Static Random-Access Memory (SRAM), which is a critical circuit component in technology development. A 6-transistor SRAM cell comprises two bistable, cross-coupled CMOS inverters to store a data bit, and two access MOSFETs to access the stored data for read and write operations. Each CMOS inverter is formed of a serially connected NFET and PFET device, which have a commonly connected source/drain layer and commonly connected gate regions. Technology nodes of 7 nm and beyond will require an increasingly tighter SRAM layout using shared trench silicide (TS) contact trenches to commonly connect source/drain layers of CMOS devices. For these applications, low contact resistance (e.g., <2.5×10−9 Ω·cm−2) is crucial to device performance. By using dual trench epitaxial and silicide layers within TS contact trenches, the contact resistance for the common source/drain layers of NFET and PFET devices can be optimized and reduced below 1.0×10−9 Ω·cm−2. However, current TS trench fabrication techniques do not provide for different (dual) epitaxial and silicide layers to be fabricated for shared TS trenches for common source/drain layers of NFET and PFET devices.